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Be a member of a high performance RTL team working at the block level and full-chip level.
Knowledgeable about RTL design best-practices, Clock domain crossing, Logical equivalence, LINT etc.
Responsibilities: Project execution, status reporting, designing with Verilog at the block level and full-chip level.
Knowledgeable about RTL design best-practices, Clock domain crossing, Logical equivalence, LINT etc.
Responsibilities: Project execution, status reporting, designing with Verilog at the block level and full-chip level.
Location : Bangalore , Andhra Pradesh , Chennai , Hyderabad , MadyaPradesh , Maharashtra ,
Experience : Freshers
Educational Qualification: Any Graduate
Job Description:
Sound knowledge of digital design, Verilog HDL and Design Best practices.
Working knowledge of the Clock Domain Crossing (CDC) tools, Formal Verification tools and ASIC/FPGA synthesis tools.
Knowledge of version control software like CVS or Perforce.
Interpersonal skills to work in a Cross Functional Team (CFT); Good communication skills; Team player
Sound knowledge of digital design, Verilog HDL and Design Best practices.
Working knowledge of the Clock Domain Crossing (CDC) tools, Formal Verification tools and ASIC/FPGA synthesis tools.
Knowledge of version control software like CVS or Perforce.
Interpersonal skills to work in a Cross Functional Team (CFT); Good communication skills; Team player
To Apply Click here
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